pcil Project Status
Project File: PCIL.xise Parser Errors: No Errors
Module Name: pcil Implementation State: New
Target Device: xc95144xl-10TQ144
  • Errors:
 
Product Version:ISE 14.6
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
CPLD Fitter Report (Text)     
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateSo 9. Sep 13:25:43 2018
Post-Fit Simulation Model Report  

Date Generated: 09/09/2018 - 13:26:01