Prometheus "Fire Storm" upgrade =============================== V0.5 15-04-2006 The Prometheus CPLD upgrade is introducing very basic changes in the CPLD firmware. Therefore a new manufacturer / product ID is chosen to avoid confusion with old versions of the PCI software. Manufacturer ID: 0x0e3b (3643) Product ID : 0xc8 (200) Memory layout: The Prometheus is autoconfiguring as 512MB Zorro III card. This 512MB region is divided into four different parts. Their offsets are given relative to the Prometheus base address: Ziii start Ziii end access type size PCI start PCI end 0x00000000 - 0x1fbfffff memory region 508MB 0x00000000 - 0x1fbfffff 0x1fc00000 - 0x1fcfffff config0 region 1MB 0x00000000 - 0x000fffff 0x1fd00000 - 0x1fdfffff config1 region 1MB 0x00000000 - 0x000fffff 0x1fe00000 - 0x1fffffff I/O region 2MB 0x00000000 - 0x001fffff Please note: The PCI access type (memory, io or config) is defined by the Zorro III offset. On PCI, all four address space are in parallel. Memory region ============= Within this region, only memory read / write commands are posted. The memory region is 508MB sized and can be addressed linearly without any banking mechanisms. Please note: the DMA buffer memory (aka the gfx card) should be located into the lowest 16MB region of this block. Many PCI sound cards can only do 24bit DMA and only access this 16MB block. I/O region ========== Intended for I/O based PCI cards; only I/O read / write commands are posted. The I/O area is 2MB sized. Please note: PCI address bits A[31:20] are set to zero when the I/O region is being accessed. Config0 region ============== Used only for configuration of PCI cards which are located on the primary PCI bus (i.e. on the PCI connectors of the Prometheus). Accesses done here are mapped to configuration read / write commands; the bus access will be a configuration cycle of type 0. Besides, the Prometheus board control register is implemented in this region (details see below). The following convention MUST be followed, otherwise bus contentions may occur! A[31:24] : must be zero A[23:20] : must be zero A[19:16] : only one of these four address lines may be "1" at a time (1,2,4,8) ALL OTHER COMBINATIONS ARE RESERVED! These lines select one of the four PCI slots on the base board. A[15:11] : must be zero A[10:8] : selects a certain function of a multifunction card A[7:2] : selects the configuration registers A[1:0] : depends on the access mode (byte/word/longword) A special masking logic inside the CPLD will automagically set PCI address bits A[28:20] to zero during configuration accesses. A[31:29] are always zero when accessing the PCI bus by Zorro III accesses. Examples: peek 0x60010000 w h -> read device ID of function 0 of first PCI card peek 0x60010002 w h -> read vendor ID of function 0 of first PCI card peek 0x60020000 l h -> read both IDs from second PCI card peek 0x60040000 l h -> same for third PCI card peek 0x60080000 l h -> same for fourth PCI card Control register: accesses are made in CFG0 area with A[15] = 1 (offset 0x60008000). This register is read / write. D31: PCI RESET#, initialized to "0", set to "1" for normal operation. PCI bus can be reset by writing "1", "0", "1" sequence independently from Amiga system. Please mind that /IORST will always put PCI bus to reset state which is kept until "1" is written into this register. QUESTION: is this reasonable? With a Sonnet7200 running one cannot reset the Classic AMIGA without killing the PPC. D30: PCI interrupt enable, initialized to "0", set to "1" to get PCI interrupts routed to Zorro bus. Please mind that /IORST will always disable PCI interrupts to keep mad PCI cards from hanging up the Amiga system. D29: PCI interrupt status; "0" means PCI int is active, "1" inactive. Config1 region ============== Used only for configuration of non-primary PCI busses behind PCI-PCI bridges. Accesses done here are mapped to configuration read / write commands; the bus cycle will be a configuration cycle of type 1. The following convention MUST be followed: A[31:24] : must be zero A[23:22] : must be zero A[21] : must be one (distinguish between Config0 and Config1) A[20] : must be zero A[29:16] : selects the PCI bus to access (must not be zero) A[15:11] : selects the PCI device on the bus A[10:8] : selects the function within a device A[7:2] : selects the configuration register A[1:0] : depends on the access mode (byte/word/longword) Please note: due to the masking logic setting PCI address bits A[28:20] to zero during configuration accesses, the number of supported PCI busses is limited to 7. Bus number 0 is illegal for a Config1 cycle, as zero is the host bus accessed by Config0 cycles. Examples: 0x60210000 -> PCI bus 1, device 0, function 0, register 0 0x60220804 -> PCI bus 2, device 1, function 0, register 1 0x60221004 -> PCI bus 2, device 2, function 0, register 1 Proposal: There should be only one Read_config() and Write_config() function, which hides this mechanism. Depending on the PCI bus number, either a Config0 or Config1 cycle is started. In case of Config0, one must only allow accesses to the four PCI slots, and return 0xffffffff in all other cases. PCI bus numbers greater than 15 should also be masked in software and return 0xffffffff on reads; writes should be void. RETRY mechanism =============== The new Fire Storm upgrade supports a simple RETRY mechanism for accesses from Zorro III to PCI. Due to timing constraints on the Zorro III bus it is advisable to access known slow devices only with PCI-PCI DMA disabled. For the software side no changes are needed; in case a PCI device does issue a RETRY situation, the Prometheus CPLDs will repeat the bus access immediately. If a RETRY fails within the timeout of Zorro III, a Bus Error will occur on Zorro III. Cards known to produce RETRYs are: - slow gfx cards when accessing onboard BIOS ROM - PCI-PCI bridges, especially on CFG cycles on the PCI bus behind the bridge