First of all, apologies for the long delayed publication of Prometheus Open Source version. Life has its own rules.
Anyway, here we are.
During bugfixing the original version of Prometheus code, I made a small description of the bug, as well as how to fix it. Fortunately, it surviced in some old backup, so I include it here for completeness.
It may help to understand the new (VHDL) version of the code a bit.
For all out there, with a genuine firmware in their Prometheus cards, you can find an archive with a bugfixer version of the firmware. You will need a download cable for legacy Altera CPLDs, and a version of the IDE from Altera supporting programming POF files (like MAX+plus II , but be aware, you need a license file to use it, it should be available from Altera as kind of legacy tool anyhow).
Please mind that the new firmware uses a new memory layout to accomodate for PCI bridges correctly.
The old drivers won't work anymore with the new firmware in place.
There are two JTAG connectors on the card, one for each CPLD. They are labeled with "CN6" and "CN7", but may not be populated (a standard 2x3 2.54mm pitch pinheader will do the job). Pin 1 is marked by a rectangle, it faces downwards to the CPLD, with Zorro connector facing downwards.
Pin 1 - TDO
Pin 2 - TCK
Pin 3 - TMS
Pin 4 - TDI
Pin 5 - GND
Pin 6 - Vcc
Please note: if you are unsure about pinout, or how to program the firmware, DON'T do any experiments and ask later - ask before risking your board. I can try to help, as time permits.
The prom_cl27.pof file is programmed in the lower CPLD by CN6, the prom_ch52i.pof goes into the upper CPLD by CN7.
Legal disclaimer: use the new firmware on your own risk.
In case you want to write some own code, there is also a short documentation available for the new firmware.
Guess that's what you are here for. I have started translating the whole legacy firmware design (which is a mixture
of graphical schematics and text files, fixed for Altera chips, in generic VHDL. I ended up with a complete simulation
testbench, and code which should (more or less) directly compile into a working bitfile.
For download, a complete set of VHDL source and testbenches are available here.
Please carefully read the license and the documentation (both also included in the ZIP archive) before using the code.
Just having some source code to play with, with no real hardware is no fun.
That's why you may find the second part of the old project to be useful.
It is a completely routed four layer board, implementing a Prometheus in Xilinx XC95144Xl CPLDs.
If you intend to build your own, I have stock of PCI connectors, 5.25" power connectors and 66MHz oscillators.
Just ask me, if you need some.
The BRD file (Eagle V6.x) is suitable for production, schematics is included as PDF.
Please mind the license for this board before using it.
Legal disclaimer: use the board design on your own risk.